Gate-Recessed Normally OFF GaN MOSHEMT With High-Temperature Oxidation/Wet Etching Using LPCVD Si3N4 as the Mask

A gate-recessed normally OFF GaN metal–oxide–semiconductor high-electron-mobility transistor on silicon substrate has been fabricated using a self-terminated, plasma-free oxidation and wet etching process with pre-recess low-pressure chemical vapor deposition (LPCVD) Si
₃
N
₄
passivation layer. The LPCVD Si
₃
N
₄
serves the dual role of gate-recess mask and passivation layer. Unlike conventional oxidation etching process using Si
₃
N
₄
as post gate-recess passivation, the gate channel region was prevented from additional plasma bombardment during the gate window re-opening. As a result, a high-effective channel mobility of 843
$\text {cm}^{\text {2}} / \text {V}\cdot \text {s}$
, and low-channel resistance of
$0.89~\Omega \cdot \text {mm}$
are achieved for a normally OFF channel with
${L}_{G} = \text {1.5}\,\,\mu \text{m}$
. For
$\text {3}~\mu \text{m}~{L}_{\text {GD}}$
, the fabricated devices exhibit a threshold voltage (
${V}_{\text {th}}$
) of 1.35 V, a maximum drain current of ~500 mA/mm, a high ON/ OFF current ratio of ~10
¹⁰
, and 560-V OFF-state breakdown voltage together with a low-forward gate leakage current of ~10
⁻⁷
mA/mm up to 10 V. A high Baliga’s figure of merit of 1.26 GW/cm
²
is achieved in devices with 10-
$\mu \text{m}$
gate–drain distance.