Fault tolerant dynamic XY-YX routing algorithm for network on-chip architecture

In this paper we present a fault tolerant dynamic XY-YX routing algorithm for 2-D mesh based NoCs. Proposed routing algorithm uses both XY and YX algorithms dynamically and provides reliable on-chip communication in the presence of single or multiple faults appear either at border or middle tiles of network. Proposed routing algorithm overcome the errors of existing fault tolerant routing algorithm and ensures deadlock free and live-lock free solution. Simulation results in respect to overall latency, average throughput and power consumed are calculated in NIRGAM simulator and shown in this paper.