Hardware implementation of 1-D 8-point adaptive multiple transform in post-HEVC standard

Despite the coding efficiency improvement cognized per HEVC standard, researchers are still devoting so much efforts for further enhancements. The latest result of ITU-T and ISO/IEC collaboration was the definition of a new standardization initiative beyond HEVC which is POST-HEVC standard. It is actually under development and scheduled to be completed in 2020. It offers many contributions specifically in the transform module. In fact, it has introduced a new approach called Adaptive Multiple Transform (AMT) which raises the issue of additional computational complexity. This work proposes hardware architectures of the 1-D 8-point Adaptive Multiple Transform for all transform types. This theme is innovative since it was not dealt with before. In this paper two transform implementations aspects are detailed and compared. The first method is based on using Altera multipliers (LPM) and the second one exploits correlation and symmetry properties in order to reduce matrix multiplications complexity. The adopted method was implemented in VHDL and it is capable to process at 288 MHZ under a Stratix III device. The number of execution cycles of this architecture can reach a maximum of 12 cycles when 8-point-1D-DCT-VIII is computed.