FRAM cell design with high immunity to fatigue and imprint for 0.5 /spl mu/m 3 V 1T1C 1 Mbit FRAM

A new ferroelectric random access memory (FRAM) cell design with high immunity to fatigue and imprint has been proposed in order to achieve a megabit class FRAM with 1T1C cell structure, and has been applied to a 1 M bit FRAM operated from a 3(V) supply with 1T1C cell structure, 0.5(/spl mu/m) rule and 3(/spl mu/m/sup 2/) capacitor area. The simulation result and imprint data predict a seven order imprint lifetime improvement compared with the conventional scheme. A pseudo after PL pulse scheme has also been presented to accelerate the slow read/write cycle time of after PL pulse.