New channel engineering for sub-100 nm MOS devices considering both carrier velocity overshoot and statistical performance fluctuations

We introduce a new channel engineering design for nano-region SOI and bulk MOSFETs taking into account both carrier velocity overshoot and statistical performance fluctuations. For types of both device, in the high gate drive region, the high field carrier velocity /spl upsi//sub e/ is not degraded at channel dopant density N/sub a/ lower than 1/spl times/10/sup 17/ cm/sup -3/, according to an experimental universal relationship between /spl upsi//sub e/ and the low field mobility. On the other hand, there is a most suitable N/sub a/ condition for suppression of statistical threshold voltage fluctuations. This most suitable N/sub a/ is slightly higher for SOI devices than that for bulk MOSFETs, but it is lower than 1/spl times/10/sup 17/ cm/sup -3/ in both cases. Therefore, this most suitable N/sub a/ condition is consistent with the above N/sub a/ condition for carrier velocity. Consequently, new N/sub a/ conditions for nano region devices are introduced in this study. N/sub a/ should be designed to be of the order of 1/spl times/10/sup 16/ cm/sup -3/ rather than rising by the usual scaling rule, but it is necessary to suppress the short channel effects of SOI and bulk MOSFETs by scaling down the SOI thickness, and to use source/drain junction depth scaling or surface low impurity structures in bulk MOSFETs, respectively.