High-speed table lookup engine for IPv6 longest prefix match

This paper presents a hardware table-lookup (TLU) engine that allows the real-time operation of complicated TLU for telecommunications such as the longest prefix match (LPM) in IPv6 (128 bit-length address) protocol. The engine consists of a PLD (programmable logic device) and eight CAM (content addressable memory) chips which are divided into several groups. When actual TLU is performed, the entries in each CAM group are searched simultaneously, and the best entry candidate in each group is selected by a priority encoder which is implemented in the PLD. This grouping method with the priority encoder is the key to the scalability of the engine. We show that a TLU engine based on the above architecture achieves significantly better performance than those based on conventional software algorithms, especially in the case of a large number of entries. Furthermore, we note that our engine can support an over 300-K entry 2.5 Mpps line-rate LPM.