Smart auto-correction methodology using assertions and dynamic partial reconfiguration

When using FPGAs for testing, error correction takes a lot of time, since a design has to be recompiled after changing. In order to fix the errors online, without recompiling the design, we propose to use mutations for error correction in reconfigurable FPGAs. The errors are detected by using synthesized Verilog assertions. We show the effectiveness of the proposed method by injecting various errors and comparing the performance versus the conventional methods. The results show that hardware overhead is small and errors can be corrected in reasonable time even for large circuits.