A 2M1M Crossbar Architecture: Memory

Memristor crossbar architectures are considered as one of the most promising platforms for future memory, logic, and in-memory computing applications. This paper presents a 2M1M crossbar architecture, capable of memory and logic applications, based on a transistor-less memory cell, which behaves as a switching circuit. The proposed memory cell consists of two access and one target memristors that utilize a gating structure by access devices to reduce sneak path effect. This paper has considerably lower wiring density and lower number of memristors per bit compared with its peers. Therefore, it can be a suitable structure for high-density memory and logic applications. In addition to its in-memory computing capabilities, 2M1M structure as a memory offers higher density and less energy consumption in comparison with conventional CMOS-based static random access memory. In comparison with previous works, simulation results show significant improvements in basic implementation costs of the memory cell in terms of write time (1.11 ns), read time (200 ps), density (80 Gb/cm
²
), energy consumption (23.2 × 10
^-3
fJ/bit), and wiring complexity. Also, it has a sneak path current of 90-nA per memory cell operation which is considerably lower compared with its peers.