A 2.4-GHz RF Fractional- ${N}$ Synthesizer With BW $= 0.25f_{\mathrm{ REF}}$

A fractional-N synthesizer architecture incorporates a 35-tap finite impulse response filter that suppresses the ΣA noise, but does not affect the loop bandwidth (BW). Employing a three-stage ring oscillator and operating with a 22.6-MHz reference frequency, the synthesizer achieves a BW of around 5.6 MHz with a power consumption of 10 mW. Realized in 45-nm digital CMOS technology, the synthesizer exhibits a phase noise of -121.4 dBc/Hz at 10-MHz offset and an integrated jitter of 1.5 psrms.