Formal Probabilistic Analysis of Low Latency Approximate Adders

Approximate computing is an emerging trend in hardware and software design that leverages upon the inherent tolerance for inaccuracy in applications to optimize their power consumption, latency, and area. Due to the widespread usage of adders in digital hardware designs, numerous approximate adders, offering various error margins and area, latency and power constraints, have been proposed. Probabilistic error analysis of these adders holds a significant step in selecting an appropriate approximate adder for a given application. Traditionally, this analysis has been conducted using Monte-Carlo simulations or analytical analysis, which do not ascertain a sound and complete analysis. In order to overcome these limitations, we propose to use interactive theorem proving for error analysis of approximate adders. For this purpose, we present a higher-order-logic formalization of probability distributions and error related events encountered in approximate adders that comprise of subadder units, based on a probability theory formalization available in the HOL4 theorem prover. We also propose an algorithm for analyzing the probability of error as a metric for accurate comparison for high-speed, low-latency approximate adders with uniformly distributed inputs. For illustration purposes, we present the formal error analysis of three of the most widely acclaimed approximate adders, i.e., error tolerant adder-I, accuracy configurable adder, and generic accuracy configurable adder.