AXI over Ethernet; a protocol for the monitoring and control of FPGA clusters

AXI over Ethernet (AXIoE) is a protocol designed to extend guaranteed in-order accesses to the memory-mapped slave registers on an FPGA to a master CPU that is located elsewhere on a local area network. AXIoE was designed for use in the Square Kilometre Array (SKA) radio telescope Central Signal Processors (CSP) to provide monitor and control functionality from a few client machines to hundreds of FPGA over a dedicated 1Gb Ethernet network. The protocol has an asymmetric design such that the AXIoE server is simple, and implementable on an FPGA with few RAM and logic resources. Consequentially the responsibility for all communication error recovery is assumed by the AXIoE client machine. This approach is different to the standard choice of TCP, where both the client and server end-points participate equally in the bidirectional error recovery. AXIoE introduces conditional execution to help minimise the detrimental effect of latency, and improve network throughput. The COND bit is used to mark transactions as conditional on the successful execution of the previous transaction. This permits a try-catch style of programming that promotes the streaming of groups of bus transactions. This paper briefly describes the AXIoE protocol, its components, and features, with discussion of the design choices and their intent.