An FPGA-in-the-loop approach for HDL motor controller verification

This paper presents a solution to address verification-related challenges during the design and validation for motor control applications that call for joint simulation of the control algorithm and the motor. One method used previously involved playback of a prerecorded motor response in order to get around a lack of an HDL model for the motor, resulting in erroneous results. To circumvent this, we present a workflow approach using FPGA-in-the-Loop simulation (FIL), which configures an FPGA with the HDL design and uses it as a computation block for closed-loop simulation. The approach is illustrated to implement, test, and validate two control schemes: a vector based Field Oriented Control (FOC) and the scalar voltage by frequency (V/f) algorithms on a permanent magnet synchronous machine. The proposed approach is useful to provide validation before hardware implementation.