One micron redistribution for fan-out wafer level packaging

Fan-Out wafer level packaging has seen rapid adoption over the last few years due to its form factor, performance, and cost advantages compared to 3D packaging techniques. Redistribution layers (RDL) are used to route the very high density connections on the chip to the much lower density connections of the substrate. Multiple layers of RDL are required in order to match the line density of the chip. This in turn increases the cost of the total package. Decreasing the metal line width for RDL supports reducing the number of redistribution levels and decreasing the total packaging cost. Reducing the RDL width requires tightening of requirements for the lithography tool and the photoresist process. Also, electroplating and etching processes need to be enhanced. This study investigates creation of RDL structures using a through resist electroplating process. A test vehicle was designed that contains various test structures used to characterize the process. This includes metrology structures for in-line monitoring, CD-SEM measurements, and comb and serpentine electrical test structures. The process starts with the deposition of a Cu seed layer needed for electroplating followed by lithography, electroplating, resist strip and Cu seed removal. The minimum thickness of the seed layer is constrained since the uniformity of the electroplating process also depends on the resistance and thus thickness of this layer. This thickness in turn has a large impact on line fidelity after removal of the Cu seed at the end of the process. In order to fabricate RDL lines with sufficient low resistance the plating thickness needs to be maximized. This translates to maximizing the aspect ratio of the photoresist pattern. In order to minimize the CD loss by Cu seed etching the wet process has to be controlled carefully. The lithography process window must have a large depth of focus in order to accommodate local height variation due to wafer topography in Fan-Out packaging. The optical lithography tool used in this study has a variable numerical aperture (NA) that can be optimized to maximize depth of focus while maintaining resolution performance in photoresist. After completing the development of the 1 μm RDL process the electrical performance was validated with meandercomb electrical test structures. The results show that lithography needs to be performed at the isofocal setpoint in order to obtain the optimal depth of focus of 7.5μm. Seed etch will reduce the Cu linewidth by 300 to 500nm and an offset in lithography CD may be required to compensate this loss. With optimal conditions good electrical yield is obtained for 1.0μm L/S meandercomb test structures.