A pure hardware k-SAT solver architecture for FPGA based on generic tree-search

SAT (Boolean SATisfiability Problem) is a well studied type of NP-complete problem. Most SAT solvers rely on software implemented tree-search based algorithms. These algorithms, basically sequential or weakly parallel, are most often ineffective when dealing with large scale instances of SAT due to the large search space to be explored in order to find one solution. Despite several improvements and heuristics being proposed for this kind of approach, the fact remains that in real problems, the computational cost continues to be prohibitive. To improve SAT solvers performance, a new trend has emerged in the late years, introducing hardware acceleration. The proposed architectures are in general hybrid, combining software and hardware parts dedicated respectively to the decisional and hard-computional parts of the algorithm. Still, most the hybrid approaches remain constrained by their limited data-access bandwith capacity. In this paper, we propose a new approach, entirely based on hardware and not depending on the SAT-instance to be solved (treated as data). It is fully configurable at synthesis in regard to the level of parallel computation and parallel buffering, as to the size of the SAT instance that can be processed (maximal number of variables and maximal clause length, the total number of clauses being unlimited). One of the main goals is to allow a more effective use of the hardware computational power by reducing the dependence to data contained in low bandwith data storage (such as RAM).