SAR TDC architecture for one-shot timing measurement with full digital implementation

This paper proposes a successive approximation register (SAR) time-to-digital converter (TDC) architecture capable of measuring the timing difference between two single-shot signals with full digital FPGA. The SAR TDC is suitable for multi-channel timing built-out self-test (BOST) implementation on an FPGA chip. In order to reduce the number of buffers and DFFs in a conventional Flash TDC or Vernier TDC, the SAR architecture is applied. However, the SAR TDC can measure only the repetitive clock timing, and it cannot measure the single-shot timing signal. So first we employ trigger circuits in front of the SAR TDC to measure the single-shot timing, but the trigger circuits include some analog circuits so that its digital FPGA implementation is difficult. Then we propose here an SAR-TDC architecture that enables the single-shot timing using ring oscillators, which leads to its full digital FPGA implementation.