Diagnosis via arithmetic circuit compilation of Bayesian network and calculation on FPGA

Aircrafts, especially the Unmanned Aerial Vehicle (UAV) are always operating in environments filled with expectations and unforeseen occasions. In addition, hardware and software failures caused by design defects are inevitable [1]. In order to avoid catastrophic failure, we must locate the failure immediately in working condition. That means real-time diagnosis. Bayesian inference has been well established in the area of diagnosis and health management. In this paper, we come up with a method to take advantage of FPGA to implement Bayesian inference, which has the features of hardware programmable and the ability of parallel computing. Therefore, we compile the Bayesian Network into arithmetic circuit, and then evaluate the arithmetic circuit on FPGA.