Evaluating the Impact of the Instruction Set on Microprocessor Reliability to Soft Errors

Reliability in microprocessors is a concern. There are many techniques that add spatial and temporal redundancy, with the goal of increasing the error detection and correction capabilities of the system. In this paper, we present a methodology to estimate the intrinsic reliability of the instruction set architecture of a given processor. By analyzing the internal encoding of the instructions and their relations, an initial estimate of the silent data corruption rate that a certain architecture may suffer due to soft errors is obtained. The results provided by this methodology can be used to compare the intrinsic reliability of different processors and help decide the best protection technique in each case.