FPGA implementation using Renoir tools: application for bit timing logic (BTL) synthesis of controller area network with 100% free error

Logic synthesis using VHDL simplifies considerably logic circuit design. However, when the application requires a few thousand lines of VHDL code, it is very beneficial to use graphic software that can produce the VHDL code. But, it is always necessary to master the VHDL language. In this paper we have studied VHDL generated with three basic processes of the Renoir state machine. An application for designing, synthesizing and implementing a bit timing logic of an ISO normalized controller area network (CAN) is given. It has been tested with 100% free error.