Test and design for testability of reconvergent fan-out CMOS logic networks

The authors address the robustness of adjacent vector sequences in irredundant RFO (reconvergent fan-out) logic networks made up of primitive CMOS (NAND, NOR) and fully complemented MOS (FCMOS) gates. RFO structures in which these sequences are robust are defined, and a DFT (design-for-testability) method for solving the remaining problems is described. It is shown that a large percentage of stuck-open faults are detected by adjacent vector sequences. The robustness of the sequences is guaranteed in many cases.<
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