A high throughput rate and low circuit complexity QAM channel equalizer design based on bit serial scheme

In this paper, a novel VLSI design for an all digital QAM channel equalizer is presented. We adopted a decision-feedback equalizer (DFE) structure to combat the inter-symbol-interference (ISI) induced during high speed data communication. The equalizer consists mainly of eight transversal adaptive filters and slicers. Since the adaptive filter along with the slicer will form a nonlinear feedback path, the resultant recursive computing often leads to a severe performance bottleneck. To overcome this, a bit serial, MSB first computing scheme based on distributed arithmetic and signed digit number system techniques was developed. In our scheme, the next symbol's equalization can be started as soon as the MSD of the current symbol is obtained. This leads to a computation overlap between successive symbol's equalization and can effectively improve the baud rate. The circuit complexity, however, is still kept low with the help of fine grain pipelining. With careful arrangement of data flow, an efficient systolic array design with 100% utilization and suitable for VLSI implementation is derived. The design architecture is also scalable in that the initiation interval between the processing of two consecutive symbols is a constant of 5+[m/4] clocks (in the delayed sign LMS case) and the hardware complexity is of order 2/spl middot/m/spl middot/(n+1), where m and n are tap order and word length.