A new hybrid PWM for two parallel connected interleaved two-level inverter to reduce output current ripple

This paper proposes a new hybrid carrier-based PWM technique for parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) analyzed as a single 3L inverter for line current ripple reduction. The carriers are interleaved to reduce the load side harmonics. However, this allows circulating current to flow between the VSIs. Using the proposed PWM technique, the circulating current is also kept lower than the conventional sinusoidal (SPWM) and space-vector PWM (SVPWM) techniques. Simulation and experimental results justifies the aforementioned statements.