Self-calibrating hybrid analog CMOS co-site interference canceller

A continuous-time analog CMOS adaptive processor circuit is combined with high-power linear attenuators to implement a self-calibrating co-site interference canceller that achieves >40 dB cancellation for a +14 dBm interference level over a 30-88 MHz band. The analog CMOS adaptive processor implements the least mean square (LMS) error learning algorithm. A CMOS interference canceller is also demonstrated that is capable of cancelling multiple interfering signals simultaneously. The multiple interference CMOS co-site canceller demonstrated a frequency of operation of 80 MHz, an adaptivity of 60 dB, a minimum notch width of 25 kHz, a minimum adapt time constant of 25 /spl mu/s, and the simultaneous cancellation of two CW interferers.