Implementation of a novel 2-stage DFT structure for CMOS pixel sensors utilizing on-chip CP-PLL clock (for retinal implant system)

A novel 2-stage testing structure for CMOS pixel sensor (CPS) is proposed here. The test stimuli are based on applying the electrical pulses instead of light stimuli on photosensitive area, for pure electrical test. The voltage stimuli applied is generated by charge-pump phase locked loop (CP-PLL) which is used here as on-chip clock, exploiting the dual role. Existing charge-pump circuit as stimulator and voltage controlled oscillator as measuring device is utilized, resulting in less area overhead. Detection of faults in all the blocks with generalized test sequence is the principle advantage. Moreover the testing strategy is applied in digital blocks only with analog blocks intact, ensuring the characteristics of CPS and CP-PLL unaltered. At first stage functionality test is performed, followed by process deviation test at second stage. Fault simulation results revealed, high defect reportage of 98.2% and 99.32% in respective stages of testing through proposed approach.