The effect of ILD material and BPSG densification anneal on the device characteristics

We examined the effect of inter-level dielectric (ILD) and densification anneal on device characteristics, such as polysilicon (poly-Si) activation, silicide resistance, and gate oxide integrity (GOI). For the sample with PTEOS/USG/PTEOS as ILD, any significant degradation of poly-Si activation and silicide resistance was not observed. But gate oxide was severely damaged due to PID. On the other hand, the sample with HLD/BPSG/PTEOS as ILD was free from PID. However, the poly-Si activation and silicide resistance significantly varied depending on the BPSG densification anneal. Our results shows that we should make a compromise between the dopant activation and silicide resistance.