Skew optimization by combining tree-based and graph-based techniques for high performance clock routing

The clock skew is one of the major constraints for high-speed operation of synchronous integrated circuits. Therefore, it is very important to reduce the clock skew under the specified skew bound, while minimizing the cost such as total wire length. In this paper, a new efficient bounded clock skew routing method is described, which generalizes the well-known bounded skew tree method by allowing loops, i.e., link-edges can be inserted to a clock tree when they are beneficial to reduce the clock skew and/or the wire length. Furthermore, routing topology construction and wire sizing is used to reduce clock delay.