Dynamic power supply current test for CMOS SRAM

This paper presents the relationship between the dynamic power supply current and the switching behavior of an SRAM cell. Compared to a fault free cell, how the short, open and coupling faults can affect the peak value of a dynamic current pulse when a transition write is performed, is analyzed. In addition, the test for linked idempotent coupling faults is proposed. This new approach has reduced test length compared to the previous March B test. Finally the low overhead built-in current sensor that can detect a dynamic current pulse and distinguish its peak value, is proposed.