A hardware efficient VLSI implementation of MPEG-4 format conversion filters

This paper presents a new VLSI design of format conversion filters for MPEG-4 systems. The design provides the functionality of 6 format conversion FIR filters proposed by MPEG-4. The main characteristic of the design is that filter coefficients were selected for efficient VLSI implementation and short design time. By introducing the concept of efficient hardware implementation in the early stage of filter design, it was possible to reduce hardware size and design time considerably. Two full custom VLSIs each containing 3 filters have been designed in three weeks. The design implemented 6 FIR filters with total 85 tabs and 16-bit internal precision using only 150,000 transistors.