High density low power full CMOS SRAM cell technology with STI and CVD Ti/TiN barrier metal

A novel full CMOS SRAM cell had been developed for low power applications. The cell size is 5.038 /spl mu/m/sup 2/ with 0.2 /spl mu/m design rule. Extremely low standby current was achieved by adopting the continuous active patterns in the cell layout to reduce shallow trench isolation (STI) induced leakage current by minimizing the STI induced stress compared to the conventional isolated active cell. Also, the feasibility of CVD Ti/TiN barrier metal for filling the deep small contacts had been proven for the first time. An 8 Mbits low power SRAM was developed successfully using this technology.