Cut-based functional debugging for programmable systems-on-chip

Due to the growth of both design complexity and the number of gates per pin, functional debugging has emerged as a critical step in the development of a system-on-chip (SOC). Traditional approaches, such as system emulation and simulation, are becoming increasingly inadequate to address the system debugging needs. Design simulation is two to ten orders of magnitude slower than emulation and, thus, is used primarily for short, focused test sequences. Emulation has the required speed but imposes strict limitations on signal observability and controllability. We introduce a new debugging approach for programmable SOC's that leverages the complementary advantages of emulation and simulation. We propose a set of tools, transparent to both the design and debugging process, that enables the user to run long test sequences in emulation and, upon error detection, roll back to an arbitrary instance in execution time and switch over to simulation-based debugging for full design visibility and controllability. The efficacy of the developed approach is dependent upon the method for transferring the computation from one execution domain to another. Although the approach can be applied to any computational model, we have developed a suite of optimization techniques that enable computation transfer in a mixed synchronous data flow semi-infinite stream random-access machine computation model. This computation model is frequently used in many communications and multimedia SOCs. The effectiveness of the developed debugging methodology has been demonstrated on a set of multicore designs where combined emulation-simulation has been enabled with low hardware and performance overhead.