Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND memory

With the use of a device simulator, we show that an ESD protection circuit whose junction is filled with contacts is suited to a scaled STI process with thin n/sup -/ junctions with n/sup +/ being implanted from contact holes. We have confirmed by measurements of the CMOS NAND flash memory that the protection has sufficient robustness.