Analysis and compact modeling of lateral DMOS power devices under ESD stress conditions

The detailed physical mechanisms specific to 40 V LDMOS power transistors under ESD stress (gate grounded/coupled) are investigated by means of TLP measurements/HBM testing, electron emission microscopy (EMMI) measurements, and 2D device simulations. Inhomogeneous triggering caused by device topology as well as the sustained nonhomogenous current flow due to the unusual electrical behaviour are analyzed in single- and multifinger devices. An existing ESD-MOS compact model is extended according to the investigated phenomena. It successfully describes LDMOS high current behaviour.