An energy efficient and high speed double tail comparator using cadence EDA tools

Comparator is the vital building block of analog to digital converter. The need for energy efficient and high speed analog-to-digital converters is necessary for the use of dynamic regenerative comparators to improve speed and efficiency of power. Fast ADCs, such as flash ADCs, requires an energy efficient comparator with small chip area. In this work comparison is performed among the delay of single Tail comparator, Double Tail Comparator and double tail comparator for less power theoretically and practically. The sub threshold leakage of transistors has usually been very small in the off state, as gate voltage is below threshold. The leakage from all sources has increased as the technology scales down. But as voltages have been scaled down with transistor size, sub threshold leakage has become a considerable factor. Fast comparators in CMOS having the problem of less rail voltages when threshold-voltages(Vt) of the devices are not scaled at the same speed as the rail voltages of the latest CMOS techniques. The proposed work consumes less power about 290mW compared to other types of comparators. The delay for the proposed architecture proved to be 10 ns which is less compared to the other comparators.