Fabrication of 0.22 /spl mu/m triple well CMOS devices by using high energy ion implantation

We manufactured 0.22 /spl mu/m triple well CMOS by using RTA and high energy ion implantation technology which was able to control minimum lateral diffusion and gave exact projection range. In order to forecast exactly the deep buried layer's projection range, we simulated by TRIM 95, and then we proceeded with RTA (rapid thermal annealing) process for dopant activation at 1050/spl deg/C, 30s after ion implantation. We have not only varied ion implantation energy (1.5 MeV-2 MeV) but also extracted electrical device parameters and compared them with conventional twin well CMOS device parameters. Regardless of implantation energy triple well CMOS has a good latch-zip immunity and breakdown voltage. When we formed deep p-well with 2 MeV ion implantation energy, namely triple well structure, it had better electrical characteristics than twin well structure in terms of leakage current, junction breakdown voltage, subthreshold current and latch-up immunity. Finally we acquired the best process condition in triple well structure which was fabricated with energy of 2 Mev and dose of 1/spl times/10/sup 14//cm/sup 2/.