New motion estimation algorithm based on bit-plane matching and its VLSI implementation

In this paper, we present a fast motion estimation algorithm based on bit-plane matching and its hardware implementation. The proposed algorithm performs motion estimation using 1-bit planes that are extracted from a video sequence. The proposed algorithm can be realized using only simple Boolean functions and makes a cheaper and faster implementation possible, while maintaining the accuracy of motion estimation. The proposed motion estimator has been implemented in FPGA and operates fast enough to handle real time video applications such as H.261/263 and MPEG-1/2.