Architecture design of a fast symbol timing synchronization system with a shared architecture for wireless ATM

a We propose a new architecture of fast symbol timing synchronization system which consists of a received signal power detector, a correlation power detector and a peak detector. These blocks have some shared hardware blocks to reduce the hardware complexity. A two-step peak detection hardware architecture is proposed to acquire the symbol timing synchronization. The proposed design can detect the correct FFT starting point within three symbols using the first two reference symbols in wireless ATM. Consequently, the proposed system is very useful for burst data transmission in wireless LAN or wireless ATM systems. The proposed architecture is designed and verified in VHDL.