Design of a low phase distortion GaAs FET power limiter

A simple design technique for a GaAs FET limiter exhibiting minimum phase distortion is presented. The key idea in removing phase distortion by selecting an appropriate device and designing a bias circuit is based on the observed properties of the gate barrier under large-signal conditions. Some illustrative examples and simulation results are presented. The proposed technique is suitable for monolithic microwave integrated circuit (MMIC) design.<
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