FPGA systolic array GZIP compressor

In this paper we present a complete, open-source GZIP compressor implementation for FPGA based on a systolic array architecture. GZIP is one of the most utilized compression algorithms. Besides the usual use-case of compression for data storage, distributed computing systems such as Hadoop utilize compression to reduce the amount of data which is transferred between computing nodes in a cluster. However, compression with GZIP requires significant amounts of CPU processing power, negating some of the advantages of the compressed-transfer approach in distributed systems. We have designed, implemented and tested a hardware architecture and software application for compressing files using a hardware GZIP compressor. The system presented in this paper offloads GZIP compression from the host CPU to one or more systolic GZIP compression cores in FPGA, thereby reducing latency caused by compression and freeing up the CPU for other computing tasks. We implemented and evaluated a single GZIP compression core in a ML605 development board, equipped with a Xilinx Virtex 6 FPGA, utilizing Xillybus for data transfers over PCI Express. Our results indicate the peak compression throughput of our implementation is over 1.3 Gbps and an average throughput of 52 Mbps on the Calgary corpus. Our FPGA compression solution is at least twice as fast as software compression on an Intel Core i7, in all evaluated scenarios, and up to 18× faster for large files. The project source code is publicly available online
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