InP-based logic gates for low power monolithic optoelectronic circuits [InGaAs/InAlAs/InP]

This paper describes the InP-based HFET technology for the implementation of high bitrate logic gates. A novel logic gate configuration is presented based on depletion mode HFETs (DHFET) using a nonlinear negative feedback (NNFB) for optimized high speed operation. The NNFB increases the switching speed of the gates while reducing the logic HIGH output level. The functionality of this logic design approach is demonstrated in InP with an 11-stage inverter chain and an output buffer. The realization of a ring oscillator and an edge-triggered D-flip-flop are currently in progress.