A 3 V, 10 bit, 6.4 MHz switched-current CMOS A/D converter design

An experimental 6.4 MS/s CMOS A/D converter design is presented. Fully-differential first-generation switched-current circuits with common-mode feedforward were used to realize a 1.5-b/stage pipelined architecture. High sampling rate and large input bandwidth were the main design objectives. The complete ADC was simulated using a SPICE level simulator. Performance is verified by analyzing the FFT of 2048 simulated samples. With f/sub in/=3.05 MHz, the simulated SFDR=62.7 dB and SNDR=57 dB. Simulations also indicate more than 6.7 effective number of bits at f/sub in/=15.85 MHz. Thus a high input signal bandwidth is demonstrated. Power dissipation is estimated to be less than 90 mW from a 3.0 V supply. Die area is 2.7 mm/sup 2/ when implemented in a 0.8 /spl mu/m digital CMOS process.