Manufacturability and testability oriented synthesis

This paper presents a case for new generation synthesis tools that incorporate manufacturability and testability as optimization factors in addition to traditional factors such as timing, die-area, and power. A suitable approach for manufacturability oriented synthesis is the interconnect field model, which estimates yield as a function of netlist attributes. Testability oriented synthesis encompasses various design-for-test (DFT), synthesis for testability, (SFT) and the high-level test synthesis (HLTS) techniques during the synthesis process.