Relating data characteristics to transition activity in high-level static CMOS design

Significant power reduction can be obtained in the datapath of a CMOS VLSI circuit if data characteristics are carefully exploited. An improved approach that achieves such reduction by using a new model relating important data characteristics to the transition activity in static CMOS circuits is presented. Specifically, relationships between fixed-point, two's complement data and 0/spl rarr/1 transition activity in static CMOS circuits are identified. Models for computing transition activity in terms of a set of statistical parameters are developed, and their performance compared with the Dual Bit Type model. Then, the use of the relationships and models to analyze and significantly reduce 0/spl rarr/1 transition activity with little computational effort is illustrated by several, high-level synthesis examples.