A 56-bit self-timed adder for high speed asynchronous datapath

The most basic element in any data-path is the adder. Variable-time adders can take advantage of the shorter carry propagation chains that occur in practice and exhibit an operand dependent addition time. Such adders are useful in self-timed data-paths. Today the latter are widely used as they can compute in mean time, reduce power consumption, and avoid long clock connections. In this paper, a new high-performance variable-time adder based on the statistical carry look-ahead addition technique is presented. The new circuit uses carry select stages to reduce the critical path. A 56-bit adder designed in this way and realised with 0.5 /spl mu/m CMOS technology shows an average addition time of /spl sim/1.28 ns, requiring only /spl sim/2900 transistors.