VLSI architecture for fast-recovery from NBTI in SRAM cell

The main aim of the paper is to implement the recovery boosting technique for reducing the impact of Negative bias temperature instability (NBTI) in SRAM cell. Previously proposed recovery boosting technique in SRAM cells to switch over between the recovery boost into the normal operating mode within a single cycle consumes more power. In this paper, we propose the logic called Multi Threshold CMOS (MTCMOS) and Floating gate MOS (FGMOS)that are used to reduce the power consumption and reduce the stress time of PMOS transistor in SRAM cell. The recovery boosting in 6T SRAM cell is designed by MTCMOS, FGMOS logic. The design is implemented in Cadence ORCAD tool, and compare the mode transition time. It is observed that the mode change of PMOS in recovery boosting of MTCMOS based SRAM cell is faster than previous techniques.