Self-checking synchronous FSM network design for path delay faults

Growth of nanometer electronic components increases requirements to testing of the logic circuits. In frame of conventional testing becomes not enough to detect stuck-at faults at circuits' gate poles it is necessary to test timing defects. One of a convenient and popular model of timing defects is path delay faults. A technique of designing a self-checking synchronous network of Finite State Machines (FSMs) for path delay faults is suggested. Checkers observe outputs only external FSMs, i.e. FSMs output lines of which are output lines of the network at whole. Single path delay faults from inputs to outputs of each FSM are contemplated. We use a multilevel or factorized logic synthesis for monotonous (unate) realization of FSM. On output lines of the corresponding FSMs synthesized by multilevel and factorized logic synthesis are provided an unidirectional manifestation of path delay faults. Monotonous realization of FSM is obtained from the State Transition Graph (STG) description of FSMs with using the (m, n)-code for states encoding and negligible enlarge the products of STG.