Multi-bit fault tolerant design for resistive memories through dynamic partitioning

This work proposes a fault diagnosis methodology intended for resistive memories. Multiple cells of a block may suffer from stuck-at faults during repetitive write operations in resistive memory. It causes serious hindrance to large scale adoption of resistive memory. This issue is addressed through introduction of von Neumann's Cellular Automata (CA). The two single length cycle attractor CA (TACA) and single single length cycle attractor CA (SACA) are synthesized to capture the erroneous bit positions of memory blocks in run time. It ensures the correct retrieval of data and fulfills the requirement of an efficient fault tolerant resistive memory subsystem.