A noise-efficient, in-pixel readout for FET-based THz detectors with direct incremental A/D conversion

A low-noise readout interface integrated with an antenna-coupled FET-based terahertz (THz) detector is designed and fabricated in a 0.15-μm CMOS standard technology. The implemented readout includes a cascade of a preamplification noise reduction stage based on a parametric chopper amplifier, and a direct analog-to-digital conversion by means of an incremental ΣΔ converter, substituting the lock-in apparatus. The measured input referred noise of 1.6 μVrms allows preserving the FET detector noise performance. The characterization results show that the noise equivalent power (NEP) of the THz detector and readout chain is of 376 pW/√Hz at the optimal bias point while providing directly a digital output. The integrated readout chain features 65 dB maximum SNR and occupies an area of 90 × 300 μm
²
, with 80 μW power consumption from 1.8 V supply.