An Improved SOI P-Channel LDMOS With High- ${k}$ Gate Dielectric and Dual Hole-Conductive Paths

An improved p-channel lateral double-diffused MOSFET (pLDMOS) with silicon-on-insulator substrate is proposed. On one hand, the improvement is attributed to a dielectric film with high permittivity (high-k), which is employed at the silicon surface to optimize the electric field distribution. Thus, the drift region dose could be increased, while its deviation has less influence on the breakdown voltage (BV). On the other hand, an additional pLDMOS is introduced to form another hole current path, which contributes to a decreased specific ON-resistance (R
_on,sp
). The simulation results show that the proposed structure exhibits a BV of 366 V and an Ron,sp of 24 mΩ·cm
²
, at a back gate bias of -200 V. Compared with the previous one, R
_on,sp
is decreased by 39%, and the dose deviation window of the drift region for ensuring the breakdown voltage above 300 V is relaxed from ±2% to ±5%.