Engineering to the least process monitoring

To achieve both goals of drastically reducing process monitoring and maintaining high product quality, CTM/D2 (California Technology and Manufacturing Group) at Intel has taken a new approach in monitor reduction in the 0.25 /spl mu/m Flash technology development and manufacturing. D2's new methodology stems from a fundamental mindset shift to a new paradigm: Engineering to the Least Process Monitoring. Intensive process monitoring only reflects deficiencies of quality in the process design. Without eliminating root causes, any monitor reduction will be limited and transitory. By the end of 1998, D2's new initiatives resulted in a 50% reduction in monitor cost per wafer, setting a new benchmark of cost effectiveness for flash technology manufacturing at Intel. Despite the aggressive monitor restrictions, D2 was able to meet the Flash technology certification goal on schedule. In addition, both line yield and die yield of the 0.25 /spl mu/m Flash technology reached record highs by the end of 1998. These records are unprecedented in Flash manufacturing at Intel.