An investigation of power delay trade-offs for dual V/sub t/ CMOS circuits

The availability of the dual V/sub t/ CMOS process provides a practical way to achieve high performance and low leakage power dissipation for current deep submicron technology. Early work on leakage power optimization of digital circuits utilizing dual V/sub t/ devices show some promising results (Kao et al., 1997). However, due to the lack of real dual V/sub t/ process models and parameters, these works are based on simple power and delay analysis of dual V/sub t/ devices. For example, the impact of dual V/sub t/ on the short circuit power dissipation is ignored in all these works. We provide extensive HSPICE simulation results on CMOS gates and circuits from a commercial dual V/sub t/ CMOS process. The experimental results show that optimization of dual V/sub t/ circuits involves complex trade-offs between leakage power, short circuit power and performance. For example, it is observed that using lower V/sub t/ devices does not always result in a faster circuit. One of the main contributions of this paper is that it reveals some new challenges and opportunities offered by the dual V/sub t/ technology to both circuit designers and CAD software developers for circuit optimization.