An environment for exploring low power memory configurations in system level design

Presents an environment for the exploration of low-power memory configurations. The environment uses accurate models of memory energy, area and delay to evaluate different configurations. Taking the constraints specified by the user and memory profiling information from the application, the environment can optimize the memory organization for a specific application. The environment also places and routes the organizations to provide more accurate energy, area and delay estimates. Our overall memory system estimation is highly accurate, with average absolute percentage errors within 7%. Within the environment, the user can explore powerful energy/area/delay trade-offs. We present results which show energy reductions within the memory system of up to 63%.